Currently employed techniques for the semiconductor package fabrication may experience form-factor constraints associated with a higher degree of device integration into a package substrate. For example, sizable air core inductor (ACI) structures may be required for the full integration of a voltage regulator with other active components (e.g., a central processing unit (CPU)) on-die. Such technology, known as a fully integrated voltage regulator (FIVR) may be used to improve and/or replace the often used voltage regulation functionality through bulky and costly on-board devices such as inductors, capacitors and integrated circuit controllers.
The implementation of FIVR (at the silicon level) and ACI (in the package substrate) may result in the enlargement of the keep-out zone of the ball grid array (BGA) in order to ensure robust functionality of the package, e.g., in order to reduce electromagnetic interference or unwanted coupling. Accordingly, the package land side footprint for BGA input/output (I/O) and/or passive components placement may be limited.
Current solutions to accommodate the FIVR/ACI integration may include passive component count reduction and/or adoption of miniaturized components, which may affect device performance and increase package bill of materials (BOM) costs. Current solutions may also involve enlarging package size to accommodate required passive (or active) components, to enable continuous device bandwidth and I/O scaling. However, such solutions may incur package BOM cost increases and further result in an increase of the overall size of the package, which may negatively impact form-factor requirements.